Journal of VLSI Design Tools & Technology

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Table of Contents

Research Articles

CMOS Gm-C IF Filter using SCA for Dual Band Receiver Kehul A Shah, N M Devashrayee

PDF 18-36

Design and Performance Analysis of Multi-Standard CMOS LNA Using Switched Capacitor and MIM Capacitor in 180nm Technology Nishant Poras, Priyanka Goyal

PDF 37-44

Memristor Modelling for Common Source Amplifier Using 180 nm Technology Herman Al Ayubi, Navaid Z. Rizvi, Piyush Kumar Mishra

PDF 45-54

Design and Implementation of an Efficient Ternary Control Unit SS Narkhede, BS Chaudhari, GK Kharate

PDF 55-70

Effect of Inter Shell Spacing on Performance of MWCNT Bundle at 100 µm Interconnect Length Akshi Acharya, Abhishek Shrivastava, Gaurav Musalgaonkar

PDF 71-79

Development of High Impedance Current Mirror Circuit With Its Implementation Using 0.18 μm Technology Haresh P. Patani, Nilesh D. Patel

PDF 87-96

FPGA Implementation of Binary Integer Decimal based Floating Point Multiplier Priyanka Rani, Sakshi Bajaj

PDF 97-103

Implementation of LMS Calibration Algorithm for 12-Bit Pipelined ADC Vishali ., Alpana Agarwal

PDF 104-113

VHDL Implementation of 4 Bit Multipliers: Comparative Study with Vedic Multiplier M A Sayyad, U R Chaware

PDF 122-127

Development of High Slew-Rate CMOS Operational-Amplifier Chilka S Patel, Priyesh P Gandhi

PDF 128-131

Implementation of Register Access Methods for Device Configuration Using UVM Jyoti Dahiya, Neeraj K. Shukla

PDF 132-138

Implementation of Sub Parts of SAR ADC Purvi J Patel, Priyesh P Gandhi

PDF 139-147

Review Articles

A Review on Charge Pump Circuits for PLL Applications D. Shekhar, A. Raman

PDF 1-11

All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey Rajesh Yadav, Neeraj Kumar Shukla, Rajesh Gupta

PDF 12-17

A Real Time Authentication Framework Using Multi-Model Biometrics Sneha Kurhekar, Harshvardhan Upadhyay

PDF 80-86

Roles and Responsibilities of Verification Language, Verification Methodology and Verification Tool for Design Verification of a DUT Rakhi Nangia

PDF 114-121