|
Issue |
Title |
|
Vol 5, No 3 (2015) |
Development of High Slew-Rate CMOS Operational-Amplifier |
Abstract
|
Chilka S Patel, Priyesh P Gandhi |
|
Vol 6, No 3 (2016) |
Development of System for Speech Enhancement using Combinational Adaptive LMS on Reconfigurable Platform |
Abstract
|
Pradip C. Bhaskar, Prachi S. Gosavi |
|
Vol 7, No 2 (2017) |
Effect of Doping and Crystal Orientation on Channel Current for Multigate Si Nanowire FET |
Abstract
|
Habib Muhammad Nazir Ahmad, Mustafa Mohammad Shaky |
|
Vol 5, No 3 (2015) |
Effect of Inter Shell Spacing on Performance of MWCNT Bundle at 100 µm Interconnect Length |
Abstract
|
Akshi Acharya, Abhishek Shrivastava, Gaurav Musalgaonkar |
|
Vol 5, No 2 (2015) |
Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating |
Abstract
|
Sudhakar Jyothula, A. Mallikarjuna Prasad, Ajit Kumar Panda |
|
Vol 7, No 1 (2017) |
Enhancement in RMPA Parameters using Slotted Rhombus Connected Square Shaped Antenna with left Handed Metamaterial |
Abstract
|
RamKishor Sharma, Mahendra Kumar Pandey, Sandeep Kumar Agrawal |
|
Vol 5, No 3 (2015) |
FPGA Implementation of Binary Integer Decimal based Floating Point Multiplier |
Abstract
|
Priyanka Rani, Sakshi Bajaj |
|
Vol 7, No 2 (2017) |
FPGA Implementation of Multiplier-less FIR Filter to Handle Higher Frequency Signals |
Abstract
|
Srividya P. |
|
Vol 6, No 2 (2016) |
Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog |
Abstract
|
Ashima Gandhi |
|
Vol 1, No 2 - 3 (2011) |
Gain Controlled Sinusoidal Oscillator Using Current Controlled Current Conveyors |
Abstract
|
Mourina Ghosh, Subhajit Bhattacharya, Ashish Ranjam, Sajal K. Paul |
|
Vol 6, No 1 (2016) |
GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology |
Abstract
|
Jubal Saji, Shoaib Kamal |
|
Vol 6, No 1 (2016) |
Hardware Implementation of Configurable Multi Image Fusion |
Abstract
|
SS. Malwadkar, WM. Mendre, SS. Agrawal |
|
Vol 5, No 2 (2015) |
Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave |
Abstract
|
Pragya Sharma, Neeraj Kr. Shukla |
|
Vol 2, No 1 (2012) |
High-speed CMOS ADCs Design |
Abstract
|
Prashant Singh, Narendra Bahadur Singh |
|
Vol 5, No 1 (2015) |
Hybrid CMOS-SET Inverter Design for Improved Performance using Tied Body-backgate Technique |
Abstract
|
Prashant Gupta, Shashank Kumar Ranu, Manish Kumar Pandey, Aminul Islam |
|
Vol 6, No 2 (2016) |
Implementation and Simulation of High Speed Dynamic Latch Comparator for ADC |
Abstract
|
Jatin A. Jajal, Mehul L. Patel |
|
Vol 4, No 3 (2014) |
Implementation and Simulation of MOSFET Switch for Switched Capacitor Circuits |
Abstract
|
Mehul L. Patel, N. M. Devashrayee |
|
Vol 7, No 1 (2017) |
Implementation of Carry Select Adder with Reduced Area Scheme |
Abstract
|
Pinaki Satpathy |
|
Vol 6, No 1 (2016) |
Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-Simulation |
Abstract
|
Bhupendra Fataniya, Akash Mecwan, Dhaval Shah |
|
Vol 5, No 3 (2015) |
Implementation of LMS Calibration Algorithm for 12-Bit Pipelined ADC |
Abstract
|
Vishali ., Alpana Agarwal |
|
Vol 6, No 2 (2016) |
Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique |
Abstract
|
Archana Kumari, Navdeep Prashar |
|
Vol 5, No 3 (2015) |
Implementation of Register Access Methods for Device Configuration Using UVM |
Abstract
|
Jyoti Dahiya, Neeraj K. Shukla |
|
Vol 5, No 3 (2015) |
Implementation of Sub Parts of SAR ADC |
Abstract
|
Purvi J Patel, Priyesh P Gandhi |
|
Vol 6, No 2 (2016) |
Layout Design, Fabrication and Characterization of n-Channel MOSFET |
Abstract
|
Savita Maurya, Sarita Shrivastava |
|
Vol 6, No 3 (2016) |
Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers |
Abstract
|
Akash I. Mecwan, N M Devashrayee |
|
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