|
Issue |
Title |
|
Vol 3, No 2 (2013) |
Logic Optimization Algorithm based on Shannon’s Expansion: Reduction in Area, Power and Delay for Pass Gate Implementation |
Abstract
|
Usha Sandeep Mehta, Vaishali Dhare, Harikrishna Parmar, Rahul A. Shah |
|
Vol 4, No 1 (2014) |
Low Power 8-Bit Square Root Carry Select Adder Constructed By Using 8 Transistor Full Adder |
Abstract
|
A. Unmai |
|
Vol 2, No 2 (2012) |
Low Power RF QPSK MODEM Design |
Abstract
|
Rupam Goswami, Prashant Singh, Narendra Bahadur Singh |
|
Vol 7, No 2 (2017) |
Low-Offset High Speed CMOS Voltage Comparator |
Abstract
|
Rohitkumar M. Joshi, Priyesh P. Gandhi |
|
Vol 7, No 1 (2017) |
Low-Power Design of Content Addressable Memory using Master Slave Match Line Architecture |
Abstract
|
Boda Venkata Lakshmi, Boggavarapu Satish Kumar |
|
Vol 2, No 3 (2012) |
Low-Voltage Low-Power Single Supply Rail-to-Rail High Resolution Comparator in 0.18 µm CMOS Technology |
Abstract
|
Anil K. Saini, Priyanka Dwivedi, Sanjay Singh |
|
Vol 5, No 3 (2015) |
Memristor Modelling for Common Source Amplifier Using 180 nm Technology |
Abstract
|
Herman Al Ayubi, Navaid Z. Rizvi, Piyush Kumar Mishra |
|
Vol 4, No 1 (2014) |
Methodology of Standard Cell Library Design in .LIB Format |
Abstract
|
Arindam Sadhu, Pritam Bhattacharjee |
|
Vol 6, No 1 (2016) |
Modeling of Voltage Buffer and Memristor Voltage Buffer Using 180 nm Technology |
Abstract
|
Herman Al Ayubi, Navaid Z. Rizvi, Piyush K. Mishra |
|
Vol 1, No 1 (2011) |
Modelling of Skin Effect in On-Chip VLSI RLC Global Interconnect |
Abstract
|
Vikas Maheshwari, Shilpi Lavania, Dr. Rajib Kar, Dr. Durbadal Mandal, Dr. A. K. Bhattacharjee |
|
Vol 4, No 3 (2014) |
Nonlinear Semiconductor Device Modeling using Neural Networks |
Abstract
|
Smrutilekha Samanta |
|
Vol 5, No 1 (2015) |
Optimized AES Implementation on Leon3 |
Abstract
|
Ashish Mishra, Sanal Kumar, Jaldeep Vasavada, Kota Solomon Raju |
|
Vol 4, No 3 (2014) |
Performance Analysis and Characterization of Shared Charge and Clocked-Latch based Comparator using 90-nm Technology |
Abstract
|
Vijay Savani, N. M. Devashrayee |
|
Vol 2, No 2 (2012) |
Performance Analysis of Fe/SiO2/Fe MTJ and Ni/Al2O3/Ni MTJ based Magnetoresistive Random Access Memories |
Abstract
|
Mayank Chakraverty, P. Arun Kumar, Harish M Kittur |
|
Vol 4, No 2 (2014) |
Performance Estimation of VLSI Design |
Abstract
|
Arindam Sadhu, Pritam Bhattacherjee, Sabnam Koley |
|
Vol 5, No 1 (2015) |
Power Analysis Comparison of Gated Diode Dram Cell Design on 32 nm Technology |
Abstract
|
Prateek Asthana, Sangeeta Mangesh |
|
Vol 1, No 1 (2011) |
Power Estimation for VLSI Circuits Using Neural Networks |
Abstract
|
Srinath B. |
|
Vol 2, No 3 (2012) |
Power Reduction at 90 nm through Circuit Level Modification |
Abstract
|
Angshuman Chakraborty, Sambhu Nath Pradhan |
|
Vol 3, No 3 (2013) |
Power-delay Product Optimal Design of Sequential Circuits Using Carbon Nanotubes |
Abstract
|
Mahesh Soni, Vineet Sahula |
|
Vol 5, No 1 (2015) |
Real Time FPGA-based Embedded Architecture of Audio Compression and Decompression Core for Multimedia System |
Abstract
|
Moumita Acharya, Shreedeep Gangopadhyay |
|
Vol 3, No 1 (2013) |
Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects |
Abstract
|
Balaji B.S. |
|
Vol 3, No 1 (2013) |
Reducing Crosstalk in Arithmetic and Logic Unit Part of a Processor |
Abstract
|
Venkatesh Kumar N., Mujeeb ulla ullah Jeelani, Anoop S. Shandilya |
|
Vol 6, No 2 (2016) |
Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM |
Abstract
|
Ashima Gandhi, Neeraj Kr. Shukla |
|
Vol 5, No 2 (2015) |
Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style |
Abstract
|
Megha Hulkey, Harshvardhan Upadhyay |
|
Vol 6, No 1 (2016) |
Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell |
Abstract
|
Jitendra Krishna Arya, Ashish Raman |
|
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