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Efficient Design of Pseudo-Random Pattern Generator with High Fault Coverage

Gargi Kaushik, Dinesh Chandra, Sangeeta Mangesh

Abstract


In this paper a comparative analysis of various test pattern generators is done in terms of power consumed .Testing is a crucial process in VLSI (Very-large-scale integration), not only it ensures proper functioning of the chip ,it also helps identify the common faults that occur as a part of VLSI fabrication. However, the power consumed during the testing process is nearly 40% higher than normal circuit operation. Various test pattern generators have been devised to reduce power starting from a simple counter, linear feedback shift registers which were later modified to ensure equally effective testing consuming less amount of power. The software used for HDL (Hardware description language) simulation in VERILOG is MODELSIM SE 6.5 whereas for power calculation QUARTUS II version 13.1 is used. For fault coverage measurements Auburn University Simulator AUSIM  is used on ISCAS’89 benchmark circuitss344 and s349.

 

Keywords: BIST, low power test, linear feedback shift register, test pattern generator, pseudo random pattern generation, Quartus II, AUSIM


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