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Analysis of Operational Transconductance Amplifier using 180 nm Technology CMOS Process

aakansha barala, Pooja Sabherwal, Nandlal Yadav

Abstract


Today, it is laborious to design an amplifier with low power utilization, high gain and high bandwidth. ICs industries are growing very fast and it is challenging for day by day growth to provide a better design with all accuracy. It is advisable to design an amplifier with an ideal way. Amplifiers are most essential unit of the analog circuitry; differential amplifier performs very well as input amplifier. Transfer characteristic with nonlinearity is drawback of this amplifier. In this paper, an operational transconductance amplifier using cadence virtuoso tool under 180 nm technologies is designed. All the simulation is performed using 2 V supply voltage. Biasing voltage -1.7 V and offset voltage is 4.3 mV is used for AC analysis.

Keywords: CMOS circuit, operational transconductance amplifier, folded cascade, virtuoso, device characteristic

Cite this Article

Aakansha barala, Pooja Sabherwal, Nandlal Yadav. Analysis of Operational Transconductance Amplifier using 180 nm Technology CMOS Process. Journal of Microelectronics and Solid State Devices. 2015; 2(2): 10–13p.


 


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