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Study of Effect of Supply Voltage and Temperature Variations on Leakage Current and Read Access Time of 6T SRAM Cell

Rajat Gupta, Amit S. Rajput, Nikhil Saxena

Abstract


Leakage Current and access time play an important role in the performance metrics of SRAM Cell. As the technology node decreases, the sub-threshold leakage and access time (during read and write operation) increases in SRAM cell where increasing of sub-threshold leakage leads to a dramatic increase in static power consumption while increasing of access time leads to a slow speed of SRAM cell. What is interesting in this paper is that investigate the difference between performance of 45 nm 6T SRAM cell and 32 nm 6T SRAM cell. Various factors which affect the  leakage current from VDD power supply and read access time such as temperature, supply voltage variations have also been explored. 6T SRAM cell has simulated at 32 and 45 nm technology PTM files for estimate the leakage current in hold mode and read delay in read mode by using HSPICE circuit simulator. Thus, 45 nm technology based 6T SRAM cell gives better result as compared to 32 nm technology based 6T SRAM cell which is described in this paper.

Keywords: Conventional 6T SRAM Cell, DIBL, sub-threshold leakage, read current, read access time

Cite this Article

Rajat Gupta, Amit S. Rajput, Nikhil Saxena. Study of Effect of Supply Voltage and Temperature Variations on Leakage Current and Read Access Time of 6T SRAM Cell. Journal of Semiconductor Devices and Circuits. 2017; 4(2): 1–5p.



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