Design and Optimization of Nano scale Double Gate SOI-MOSFET for Analog Applications Using SILVACO TCAD

Forfattere

  • Mr. Indra vijay Singh amu aligarh
  • Dr. M. S. Alam

Nøgleord:

Index Terms, DG-SOI-MOSFETs, DIBL, and Threshold voltage

Resumé

In this paper the structure effect on electrical characteristics of 60-nm double-gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor (DG-SOI-MOSFETs) is explored. These structures enable more aggressive device scaling in nano scale region because of their ability to control short channel effects. Established a scaling theory which gives guidance for the device optimization (Silicon film thickness Tsi (20nm); gate oxide thickness Tox (3nm); buried oxide thickness Tbox (200nm) and gate length LG (60nm). So that maintaining a subthreshold factor, the on/off current ratio, threshold voltage (Vth= 0.5V) and drain induced barrier lowering for a given gate length LG. Analog performance of device has been investigated interns of gm, gds, Av, ft and fmax. All these results have been simulated by using SILVACO TCAD Keywords:  Index Terms: DG-SOI-MOSFETs, DIBL, and Threshold voltage  

Forfatterbiografi

  • Mr. Indra vijay Singh, amu aligarh
    depart ment of electronics engineering AMU aligarh

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Publiceret

2011-04-01

Nummer

Årg. 2 Nr. 1 (2011)

Sektion

Research Articles

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