VLSI Transistor and Interconnect Scaling Overview

Autori

  • Pritam Bhattacharjee West Bengal University of Technology, Kolkata, India
  • Arindam Sadhu

Parole chiave:

Scaling factor ‘s’, technology or process node, Short-Channel Effects, drain-induced barrier lowering, punch through, surface scattering, velocity saturation, impact ionization, hot electrons, SOI, Floating Body, FinFET, Quantum Dot Cellular Automata

Abstract

In this paper, various types of device and interconnect scaling used for VLSI transistors are mentioned. Advanced device scaling techniques using SOI & FINFET technology are discussed for nano-devices. New technologies adopted at research level are stated here in brief.  Keywords: Scaling factor ‘s’, technology or process node, short-channel effects, drain-induced barrier lowering, punch through, surface scattering, velocity saturation, impact ionization, hot electrons, SOI, floating body, FinFET, quantum dot cellular automata

Biografia autore

  • Pritam Bhattacharjee, West Bengal University of Technology, Kolkata, India
    pursuing Ph.D at West Bengal University of Technology under Dr. Debashis De, Associate Professor, Computer Science Engineering department, WBUT

Dowloads

Pubblicato

2014-03-14

Fascicolo

V. 5 N. 1 (2014)

Sezione

Review Articles

Licenza

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