Implementation of Sense Amplifier-based D Flip-Flop using 0.25 μm and 0.18 μm Technology

著者

  • Piyush M. Bhatasana Electronics and Communication Engg Dept. Institute of Technology, Nirma University, India
  • Vijay G. Savani Nirma University image/svg+xml
  • Akash I. Mecwan Nirma University image/svg+xml

キーワード:

Johnson counter、 flip-flop、 sense amplifier、 SAFF

要旨

 The traditional flip-flops and latches suffer from the large delays and the race conditions. This paper describes a new approach to the D flip-flop design using the sense amplifier. The previous efforts in the same direction made at the 0.25 μm technology exhibit improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops. The paper discusses the flip-flop at 0.18 μm technology. The output latch of the proposed circuit can be considered as a hybrid solution between the standard NAND-based SR latch and the N-C2MOS approach. The present technology exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.Keywords: Johnson counter, flip-flop, sense amplifier, SAFF 

著者略歴

  • Piyush M. Bhatasana、 Electronics and Communication Engg Dept. Institute of Technology, Nirma University, India
    Electronics and Communication Engg Dept. Institute of Technology, Nirma University, India
  • Vijay G. Savani、 Nirma University
    Electronics and Communication Engg Dept.
  • Akash I. Mecwan、 Nirma University
    Electronics and Communication Engg Dept.

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発行日

2013-12-30

巻号

巻 4 号 3 (2013)

セクション

Research Articles

ライセンス

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