Design and Analysis of Bootstrap Sample and Hold Circuit

著者

  • Ankush Chunn DR. B.R. AMBEDKAR NATIONAL INSTITUTE OF TECHNOLOGY, JALANDHAR
  • Harsh Sohal

要旨

This paper describes the design and implementation of open-loop sample and hold-circuit using bootstrap technique, which can be used as front end sampling circuit for high-speed analog-to-digital converters. Different design criteria, viz., speed, power, resolution, linearity, noise and harmonic analysis have been dealt with. Both theoretical analysis and simulation results are carried out. The bootstrap circuit is designed and then compared in a 0.18 and 0.35 μm CMOS process. It is observed that signal-to-noise and distortion ratio (SNDR) and effective number of bits (ENOB) are higher for 0.35 μm technology. But these advantages are at the cost of higher power dissipation. Hence, there exists a trade-off between these performance metrics.Keywords: VLSI, sample and hold, track and hold

著者略歴

  • Ankush Chunn、 DR. B.R. AMBEDKAR NATIONAL INSTITUTE OF TECHNOLOGY, JALANDHAR

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発行日

2014-12-30

巻号

巻 5 号 3 (2014)

セクション

Research Articles

ライセンス

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