VLSI Transistor and Interconnect Scaling Overview

作者

  • Pritam Bhattacharjee West Bengal University of Technology, Kolkata, India
  • Arindam Sadhu

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Scaling factor ‘s’##common.commaListSeparator## technology or process node##common.commaListSeparator## Short-Channel Effects##common.commaListSeparator## drain-induced barrier lowering##common.commaListSeparator## punch through##common.commaListSeparator## surface scattering##common.commaListSeparator## velocity saturation##common.commaListSeparator## impact ionization##common.commaListSeparator## hot electrons##common.commaListSeparator## SOI##common.commaListSeparator## Floating Body##common.commaListSeparator## FinFET##common.commaListSeparator## Quantum Dot Cellular Automata

摘要

In this paper, various types of device and interconnect scaling used for VLSI transistors are mentioned. Advanced device scaling techniques using SOI & FINFET technology are discussed for nano-devices. New technologies adopted at research level are stated here in brief.  Keywords: Scaling factor ‘s’, technology or process node, short-channel effects, drain-induced barrier lowering, punch through, surface scattering, velocity saturation, impact ionization, hot electrons, SOI, floating body, FinFET, quantum dot cellular automata

作者簡介

  • ##submission.authorWithAffiliation##
    pursuing Ph.D at West Bengal University of Technology under Dr. Debashis De, Associate Professor, Computer Science Engineering department, WBUT

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出版日期

2014-03-14

期號

卷 5 期 1 (2014)

分類

Review Articles

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