Impact of Spacer Engineering on SOI Junctionless FET Performance Using TCAD Simulation

Autori

  • P. Sasikala
  • Priscilla Scarlet Department of Information Technology, Sri Sivasubramaniya Nadar College of Engineering, Chennai, India
  • K.K. Nagarajan Department of Electronics and Communication Engineering, Sri Sivasubramaniya Nadar College of Engineering, Chennai, India
  • R. Srinivasan Department of Information Technology, Sri Sivasubramaniya Nadar College of Engineering, Chennai, India

Parole chiave:

Planar, TCAD, fT, SOI junctionless FET, high-k, buried oxide (BOX)

Abstract

In this paper, the impact of spacer engineering on 10 nm gate length planar SOI (Silicon On Insulator) junctionless transistor performance is studied using Sentaurus TCAD simulator. Spacer length and spacer permittivity of the device are taken as two controllable parameters. DC performance metrics, ION, IOFF, ION/IOFF ratio, unity gain frequency (fT) and non quasi static delay (NQS) are investigated for various spacer lengths and spacer permittivity. The simulation results suggest that with high-k spacer and with minimum spacer length better ION/IOFF ratio can be achieved. fT (unity gain frequency) decreases at higher spacer lengths and at higher permittivity values. Phase delay increase with increase in frequency.Cite this Article Sasikala P, Priscilla Scarlet, Nagarajan KK, Srinivasan R. Impact of Spacer Engineering on SOI Junctionless FET Performance Using TCAD Simulation. Journal of Materials & Metallurgical Engineering. 2016; 6(2): 42–52p. 

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Pubblicato

2016-07-28

Fascicolo

V. 6 N. 2 (2016)

Sezione

Research Articles

Licenza

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