Test Time and Power Optimization of 2D SOCs Using GA and Greedy Algorithm

Authors

  • Naveen Dewan Department of Electronics and Communication Engineering, Thapar University, Patiala, Punjab
  • Prashit Aggarwal Department of Electronics and Communication Engineering, Thapar University, Patiala, Punjab
  • Harpreet Vohra Department of Electronics and Communication Engineering, Thapar University, Patiala, Punjab

Abstract

This paper presents a genetic algorithm (GA) and greedy algorithm-based solution to co-optimize test scheduling under power constraint for core-based system-on-chips (SOCs). The core testing solutions are represented as set of wrapper configurations represented in rectangular bins of width equal to the test access mechanism (TAM) bandwidth and height equal to the corresponding test time. A best fit algorithm is used for the wrapper design. Experimental results are obtained for ITC’02 benchmark SOCs. The GA algorithm provides 8% reduction in testing time as compared to the greedy algorithm.  Keywords: genetic algorithm, SOC testing, wrapper design, test scheduling, power constraintCite this Article Naveen Dewan, Prashit Aggarwal, Harpreet Vohra. Test Time and Power Optimization of 2D SOCs Using GA and Greedy Algorithm. Journal of Power Electronics and Power Systems (JoPEPS). 2015; 5(2): 63–67p.

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Published

2015-07-04

Issue

Vol. 5 No. 2 (2015)

Section

Research Articles

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