Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder

Autor/innen

  • Ankit Mitra B.P. Poddar Institute of Management and Technology

Schlagwörter:

ALU, clock gating, CPU, CMOS, FPGA, MOSFET, Spartan3E, VHDL

Abstract

The ALU is one of the most frequently accessed modules in a CPU and is utilized during most instruction executions. Hence the power consumption of the ALU is a major concern. In this paper a low power 32 bit ALU is designed using VHDL. Lower power consumption is achieved by using clock gating technique than conventional design. A carry skip adder with variable block length is used for the arithmetic unit to achieve better performance and compared with the performance of the ALU based on Ripple Carry Adder.  The design is then implemented in Xilinx Spartan 3E FPGA . The Carry Skip Adder based ALU achieves a maximum frequency of 49.48 MHz with a dynamic power dissipation of 2.18 mW when operated at 10 MHz.

Autor/innen-Biografie

  • Ankit Mitra, B.P. Poddar Institute of Management and Technology
    Ankit Mitra completed his Bachelors of technology(B.Tech) in Electronics and Communication Engineering from B.P. Poddar Institute of Management and technology in 2012. He was an active member of the Society of Optical Engineering  (SPIE)  student’s  chapter. He has consistently been among the departmental toppers throughout his undergraduate. He has qualified Graduate Aptitude in Engineering (GATE) in 2013 and currently doing independent research work in the field of Digital VLSI.

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Veröffentlicht

2013-09-05

Ausgabe

Bd. 3 Nr. 2 (2013)

Rubrik

Research Articles

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