Performance Estimation of VLSI Design

Auteurs-es

  • Arindam Sadhu Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India
  • Pritam Bhattacherjee Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India
  • Sabnam Koley Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India

Mots-clés :

Propagation delay, NMOS, PMOS, Rise Time, Fall Time, Elmore Delay, Layout.

Résumé

This paper explores performance estimation of VLSI design using simple RC delay model based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow for delay convergence is also shown.   Keyword: Propagation delay, NMOS, PMOS, Rise Time, Fall Time, Elmore Delay, Layout

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Publié

2014-08-26

Numéro

Vol. 4 No. 2 (2014)

Rubrique

Review Articles

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