Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell

Autori

  • Jitendra Krishna Arya Department of ECE, National Institute of Technology, Jalandhar, Punjab, India
  • Ashish Raman Department of ECE, National Institute of Technology, Jalandhar, Punjab, India

Abstract

VLSI design is persistently demanding for ultra-low power efficient and data stability solution. This review paper studies and analyses about various techniques to reduce leakage and dynamic power dissipation. Sleepy keeper approach, super cutoff mode, NTC method, dual-threshold approach, quiet-bitline and single bitline architecture are discussed for the power reduction. Sleepy keeper, NTC and dual-threshold approach are focused for high data stability and performance. Quite bitline architecture SRAM saves overall power compared to self-align baseline SRAM. Dynamic and leakage power reduction and read stability enhancement are reviewed and verified in 65 nm technology.   Keywords: Data stability, leakage power, dynamic power, dual threshold method, SNM: static noise marginCite this Article Jitendra Krishna Arya, Ashish Raman. Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell. Journal of VLSI Design Tools and Technology. 2016; 6(1): 73–77p.

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Pubblicato

2016-02-26

Fascicolo

V. 6 N. 1 (2016)

Sezione

Review Articles

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