Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique

Авторы

  • Archana Kumari Department of Electronics and Communication Engineering, Bahra University, Shimla-Hills, HP, India
  • Navdeep Prashar Department of Electronics and Communication Engineering, Bahra University, Shimla-Hills, HP, India

Ключевые слова:

Shift register, dual-edge triggered, flip-flop, low power, multi-threshold CMOS.

Аннотация

This paper enumerates the design of low power shift registers using dual-edge triggered flip-flop (DETFF). In the conventional shift registers, high leakage current is becoming a significant contributor to power dissipation. In order to overcome this problem, the multi-threshold complementary metal oxide semiconductor (MTCMOS) technology is used for leakage minimization in proposed designs. This technology features both low-threshold and high-threshold voltage MOSFETs. High-threshold voltage MOSFETs reduced the stand-by leakage current during the sleep mode. The conventional and proposed shift registers are presented and compared. The result shows a significant reduction in power as compared to the conventional shift registers. The shift register has been designed and simulated by using tanner v13.0 tools.  Keywords: Shift register, dual-edge triggered, flip-flop, low power, multi-threshold CMOSCite this Article Archana Kumari, Navdeep Prashar. Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique. Journal of VLSI Design Tools and Technology. 2016; 6(2):     53–61p.

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Опубликован

2016-07-06

Выпуск

Том 6 № 2 (2016)

Раздел

Research Articles

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