Low-Offset High Speed CMOS Voltage Comparator

Autores

  • Rohitkumar M. Joshi Department of Electronics & Communication, L.C. Institute of Technology, Bhandu, Gujarat, India
  • Priyesh P. Gandhi Department of Electronics & Communication, L.C. Institute of Technology, Bhandu, Gujarat, India

Resumo

A Low-Offset High Speed CMOS comparator using dynamic latch, suitable for high-speed Analog-to-Digital Converter (ADC) with high speed and low offset dissipation is presented. The design is intended to be implemented in Low-offset high speed CMOS Voltage Comparator. This circuit combines the good features of the resistive dividing comparator and the differential current sensing comparator. The design has been carried out in Tanner EDA tools, the schematic simulation is done using Schematic Editor (T-spice) using 0.18μm CMOS technology.It is found that the Offset is least dissipated in 1.8V which is 0.356mW, but it has the longest propagation delay of 1.33 ns. Keywords: dynamic latch,  CMOS comparator, differential current sensing, low-offsetCite this Article Joshii Rohitkumar M, Gandhi Priyesh P. Low-Offset High Speed CMOS Voltage Comparator. Journal of VLSI Design Tools and Technology. 2017; 7(2):      13–19p.

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Publicado

2017-07-13

Edição

Vol. 7 N.º 2 (2017)

Secção

Research Articles

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