FPGA Implementation of Multiplier-less FIR Filter to Handle Higher Frequency Signals

Auteurs-es

  • Srividya P. Department of Electronics and Communication Engineering, R.V. College of Engineering, Bengaluru, Karnataka, India

Résumé

Filtering a signal in general involves spectrum modification by blocking or allowing the required portions of the spectrum based on the frequency requirement. Filters are designed based on the requirements for manipulating the signal for a desired application. This paper focuses on the existing architectures for developing FIR filters and also describes a new method to develop a multiplier-less filter which is suitable to implement any type of FIR filter. The proposed architecture helps in area reduction and it also increases the computational speed. The proposed architecture is most suited for FPGA implementation as it does not use the conventional multiply and accumulate operations which involve the usage of more number of multipliers and adders. The proposed architecture can be used for higher frequency signals which involve a large number of filter coefficients.Keywords: FIR filter, MAC, DA based filterCite this ArticleSrividya P. FPGA Implementation of Multiplier-less FIR Filter to Handle Higher Frequency Signals. Journal of VLSI Design Tools & Technology. 2017; 7(2): 45–53p.

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Publié

2017-09-19

Numéro

Vol. 7 No. 2 (2017)

Rubrique

Review Articles

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