A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology

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  • Viajyanand Krishnan
  • Sureshkumar N Info Institute of Engineering, Coimbatore, Tamilnadu, India

Klíčová slova:

MTCMOS, full adder, full subtractor, CMOS circuit, leakage current, low power design.

Abstrakt

In CMOS logic circuits, the reduction in the threshold voltage due to voltage scaling leads to increase in the subthreshold leakage current and hence static power dissipation. Although power consumption is important for modern VLSI design, operation speed and occupied area are still the main requirements of the VLSI design. Multi threshold voltage CMOS (MTCMOS) technology is a good solution which provides a high performance and low-power design without any area overhead. MTCMOS technology provides the transistors that have low, normal and high threshold voltage. The low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. This paper describes a low-power and high speed design for full adder, full subtractor and 4×4 carry save multiplier circuits with Multi-threshold CMOS (MTCMOS) technology using Microwind EDA tool.

Stažení

Publikováno

2014-03-28

Číslo

Vol 4 No 1 (2014)

Sekce

Research Articles

Licence

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