Performance Estimation of VLSI Design

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  • Arindam Sadhu Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India
  • Pritam Bhattacherjee Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India
  • Sabnam Koley Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India

Klíčová slova:

Propagation delay, NMOS, PMOS, Rise Time, Fall Time, Elmore Delay, Layout.

Abstrakt

This paper explores performance estimation of VLSI design using simple RC delay model based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow for delay convergence is also shown.   Keyword: Propagation delay, NMOS, PMOS, Rise Time, Fall Time, Elmore Delay, Layout

Stažení

Publikováno

2014-08-26

Číslo

Vol 4 No 2 (2014)

Sekce

Review Articles

Licence

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