Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology

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  • A. K. Pathrikar Department of Electronics and Communication, DIEMS, Aurangabad, Maharashtra, India
  • Rajkumar S. Deshpande Shri. CSMCoE, Nepti, Ahmednagar, Maharashtra, India

Abstrakt

This paper proposes a review on study and analysis of an efficient fast low power 1 Kb SRAM cell using 90 and 45 nm Microwind technology. In this paper we have proposed the tentative improvement in performance parameters of SRAM cell like power dissipation, read or write speed, stability and signal to noise margin ration (SNM) using CMOS scaling.  Keywords: SRAM, CMOS scaling, MicrowindCite this Article Pathrikar A.K, Deshpande Rajkumar S. Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90 and 45 nm Microwind Technology. Journal of VLSI Design Tools and Technology (JoVDTT). 2015; 5(2): 1–3p.

Stažení

Publikováno

2015-05-06

Číslo

Vol 5 No 2 (2015)

Sekce

Review Articles

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