Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating

Abstrakt

Nowadays design of electronic circuits to meet requirements like high speed, better functionality and low power is a tedious task. Power dissipation in any circuit comprises mainly two components: static power and dynamic power. The dynamic power heavily depends on the switching activity of the circuit. During the transistor switching transitions some spikes may occur, which are called as glitches. These glitches contribute 20–70% of the dynamic power and 20% of the total power consumption. Glitches will occur at a particular candidate gate if the delay of the gate is less than the differential delay of their paths at the inputs. Numerous techniques have been proposed so far for suppression of glitches. But all these techniques target for either low power or speed. Here we propose a novel technique based on effective utilization of fast, slow and typical library cells and clock gating technology by targeting for zero dynamic power. In this paper, we have thoroughly discussed about the effects occurring due to the proposed technique on area, delay and power of the ISCAS 85 bench mark circuits using Cadence RTL compiler.   Keywords: Low power design, glitches, clock gating, multi threshold, zero leakage, zero dynamicCite this Article J.Sudhakar, A. MallikarjunaPrasad, Ajit Kumar. Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating. Journal of VLSI Design Tools and Technology (JoVDTT). 2015; 5(2): 29–37p.