Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave

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  • Pragya Sharma VLSI Group, Department of EECE, ITM University, Gurgaon, India
  • Neeraj Kr. Shukla Xinoe Sytems Pvt. Ltd, Sector 18, Gurgaon, India

Abstrakt

This paper focuses on I2C (Inter Integrated Circuit) protocol master controller. I2C protocol was originally given by Philips semiconductors so that faster devices can communicate with slower devices and also allow devices to communicate with each other over serial bus without data loss. The I2C controller provides support for a communication link between integrated circuits and memory units on a board. I2C is a bidirectional serial bus which contains two lines which are clock line and a data line SCL and SDA respectively. There are many devices which get the support from I2C bus having different addresses. In this paper, the communication between the memory which is EEPROM and FPGA Spartan 6 is shown and the device utilization summary is generated for the same. The programmed FPGA acts as the master and the memory acts as the slave. The module is designed in Verilog, implemented and simulated using Xilinx 14.7.   Keywords: EEPROM, FPGA, FSM, I2C, Spartan 6, UCF, Verilog HDLCite this Article Pragya Sharma, Neeraj Kr. Shukla, Rakhi Nangia. Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave. Journal of VLSI Design Tools and Technology (JoVDTT). 2015; 5(2):    42–48p.

Stažení

Publikováno

2015-06-07

Číslo

Vol 5 No 2 (2015)

Sekce

Research Articles

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