System Level Modeling of ISMB Quadrature Transceiver

Forfattere

  • Rupam Goswami Worked for M Tech dissertation in MEMS Design Lab at CEERI from Tezpur Central University, Tezpur, Assam, India.
  • Prashant Singh Worked for M Tech Dissertation for the degree in Microelectronics and VLSI Design in MEMS Design Lab at CEERI.
  • Narendra Bahadur Singh Senior Principal Scientist, Central Electronics Engineering Research Institute(CSIR-CEERI), Pilani, Rajasthan-333031.

Nøgleord:

Industrial, scientific and medical radio band, narrowband interference, quadrature downconversion receiver, Hilbert transform, convolution, FFT, DFT, Chebyshev filter, Matlab, Simulink

Resumé

In this paper, a new ISMB quadrature transceiver system-level design architecture is presented along with its referenced mathematical models and these were verified using state-of-the-art system modeling tools. Unlike a K-TEK’s receiver, it does not suffer from the timing and template matching problems, and it circumvents processing at high frequencies, thereby reducing the on-chip circuit complexity and power consumption. Hilbert transform has been used at the output of the demodulator for the envelope detection to get the more reliable desired signal that is also the uniqueness in the system. It also presents parallel approach to use a band-pass filter at the output of the demodulator to eliminate the d.c. component to get the desired signal. Matlab coding and Simulink system modeling were parallel done before the design of monolithic integrated circuit using CMOS technology to transfer the similar function on silicon and the objective is completed for most of the blocks. The system-level simulation, presented in this paper, shows the functional behavior of the proposed transceiver. 

Forfatterbiografi

  • Narendra Bahadur Singh, Senior Principal Scientist, Central Electronics Engineering Research Institute(CSIR-CEERI), Pilani, Rajasthan-333031.
    Deaprtment: MEMS/MS/RF CMOS IC DesignDesignation:Senior Principal ScientistTel No: +91-1596-252281, Mobile: +91 9414883889.Current R&D Area:  MEMS,Analogue,Digital, Memory,MS,RF CMOS IC Design & Testing.   Bio: More than 28 Years of R&D Experiences on Analogue (12/16 bit SA,SD,Flash & SR ADCs/DACs, PLL/VCO/Sensor’s Signal Conditioners), Digital & RF CMOS Full Custom ICs Design, PSDRAM/SRAM Full Custom Chip Design, Micro Sensors (MEMS) Design, IEEE-754 Compatible Floating Point and RISC Processor Design, AES/DES with enhanced key feature Cryptography System Design for Secured data  Communication, JPEG Codec Design, ATPG Development, QPSK/ASK/AM TRX/Modem system modelling and CMOS Circuits Design. Experience on front and back end VLSI Design tools, IC Test setup development and testing, Integration of I/O’s on FPGA and testing in board. Numerical Simulation and High Speed Device modelling. CMOS Circuit/Device/IC Process Simulation and Modeling.  Experience on semiconductor processes. Neural Networks for Pattern Learning and Fuzzy Rule based Expert System Shell development. Knowledge and extensive work experience on of all Computer languages and micro/mini/main frame/embedded systems. Experience on Management of Computers on LAN, ECAD, mail, squid and proxy servers. More than 30 papers in journals as well as international conferences. ME in Microelectronics Teaching experience in BITS. Supervised More than 27 M Tech 1 year dissertations in Microelectronics & VLSI Design and 50 B Tech/ M Sc/ MCA dissertations for six months. 

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Publiceret

2012-09-10

Nummer

Årg. 2 Nr. 2 (2012)

Sektion

Research Articles

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