Low-Voltage Low-Power Single Supply Rail-to-Rail High Resolution Comparator in 0.18 µm CMOS Technology

Forfattere

  • Anil K. Saini CSIR-Central Electronics Engineering Research Institute
  • Priyanka Dwivedi CSIR-Central Electronics Engineering Research Institute
  • Sanjay Singh CSIR-Central Electronics Engineering Research Institute

Nøgleord:

Rail-to-rail, charge pump, dynamic compartor, non-overlap clock, low voltage

Resumé

This paper presents an absolute input rail-to-rail ultrahigh-resolution comparator for low-voltage low-power applications. To enhance the input range rail-to-rail, the proposed comparator utilizes dynamic configuration with a MOSFET-only clock booster to supply a boosted voltage for pre-amplifier stage. Cadence SPICE simulations of the proposed comparator in a 0.18 μm CMOS process confirm the rail-to-rail input range with a supply voltage of 1.2 V with a decision time less than 9 ns. The dynamic power consumption of the proposed comparator is 59.3 μW with a clock frequency of 1 MHz.  

Forfatterbiografier

  • Anil K. Saini, CSIR-Central Electronics Engineering Research Institute
    ScientistIC Design GroupCEERI
  • Priyanka Dwivedi, CSIR-Central Electronics Engineering Research Institute
    Project AsistantIC Design GroupCEERI
  • Sanjay Singh, CSIR-Central Electronics Engineering Research Institute
    ScientistIC Design GroupCEERI

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Publiceret

2012-12-20

Nummer

Årg. 2 Nr. 3 (2012)

Sektion

Research Articles

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