Performance Estimation of VLSI Design

Forfattere

  • Arindam Sadhu Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India
  • Pritam Bhattacherjee Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India
  • Sabnam Koley Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India

Nøgleord:

Propagation delay, NMOS, PMOS, Rise Time, Fall Time, Elmore Delay, Layout.

Resumé

This paper explores performance estimation of VLSI design using simple RC delay model based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow for delay convergence is also shown.   Keyword: Propagation delay, NMOS, PMOS, Rise Time, Fall Time, Elmore Delay, Layout

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Publiceret

2014-08-26

Nummer

Årg. 4 Nr. 2 (2014)

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