Design of High-Speed and Low-Power Carry Skip Adder

Forfattere

  • Gutlapalli Venkatrao Department of Electronics and Communication Engineering, Geethanjali College of Engineering and Technology, Hyderabad, Telangana, India
  • Motkuri Krishna Department of Electronics and Communication Engineering, Geethanjali College of Engineering and Technology, Hyderabad, Telangana, India

Resumé

In this brief, we present a high speed and lower power consumption carry skip adder (CSKA) architecture compared with the conventional one. The increment of speed is attained by implementing concatenation and incrementation strategy to improve the efficiency of the conventional CSKA (Conv-CSKA) architecture. Instead of make use of multiplexer logic, the proposed architecture makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) combination gates for the carry skip logic. The structure possibly designed with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and power parameters of the adder. This expansion utilizes a modified parallel structure for increasing the slack time, and enabling further voltage reduction. The proposed architectures are evaluated by comparing their speed, power, and area with those of other adders using 90-nm and 45-nm static CMOS technology.   Keywords: Carry skip adder (CSKA), high performance, incrementation, concatenationCite this Article Venkatrao and Krishna. Design of High-Speed and Low-Power Carry Skip Adder. Journal of VLSI Design Tools and Technology. 2016; 6(3): 35–44p.

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Publiceret

2016-12-08

Nummer

Årg. 6 Nr. 3 (2016)

Sektion

Short Articles

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