Årg. 5 Nr. 2 (2015)

Se Årg. 5 Nr. 2 (2015)

Publiceret: 2015-05-06

Research Articles

Comparative Analysis of High Speed Comparator for A to D Converters

Priyesh P. Gandhi, Neha B. Rathod, N. M. Devashrayee

4-10
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4-Bit Magnitude Comparator Design Using Different Logic Style

Vipul Mittal, Tanushree ., Madhulika Arora, Meenakshi Yadav, Sakshi Chaudhary

16-22
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A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier

Kirti Sharma, Anushree .

23-28
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Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating

Sudhakar Jyothula, A. Mallikarjuna Prasad, Ajit Kumar Panda

29-37
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Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave

Pragya Sharma, Neeraj Kr. Shukla

42-48
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Automated Access Backdoor for UVM_REG Layer

Seep Sethi, Neeraj Kr. Shukla

49-53
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Characterization of High Performance Third Generation Current Conveyor using CMOS Technology

Megha M. Patel, Nilesh D. Patel

54-63
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Comparative Analysis of Class-AB Voltage Follower using DTMOS Transistor

Nishtha K. Patel, Nilesh D. Patel

64-70
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Design of 8 Bit High Speed Pipelined ADC

Shivani R. Patel, Priyesh P. Gandhi

71-80
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Tuning Range, Phase Noise and Jitter Analysis of Current Starved Voltage Controlled Oscillator (VCO) for Digital PLL in 45 nm CMOS Technology

Bharat H. Nagpara

81-89
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Review Articles

Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology

A. K. Pathrikar, Rajkumar S. Deshpande

1-3
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Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter

Aakansha Barala, Pooja Sabherwal, Meenakshi Yadav

11-15
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Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style

Megha Hulkey, Harshvardhan Upadhyay

38-41
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