Power Reduction at 90 nm through Circuit Level Modification

Abstract

Along with dynamic power, leakage power has turned out to be a major contributor to the overall power consumption in VLSI circuits. This problem is even more stringent in nano-scale dimension devices according to the International Technology Roadmap for Semiconductors (ITRS). As the technological advancements demand more function per device with a significant shrinking in device dimension, heat per unit area is also escalating at an elevated rate. This turns out into degradation of device material, viz., di-electric breakdown, altered component characteristics, etc. This demands additional cooling arrangements to keep the heat density to a minimal operational range. Due to increased power consumption, the battery power also gets drained at a rapid rate. This demands bulky power sources in miniature devices, which is a great hindrance in hand-held portable gadgets. Static power dissipation occurs in run time as well as in active mode of operation of the device. In this work, we have proposed a run time leakage current reduction technique for the CMOS logic circuit at 90 nm technology. As a basic building block, we have selected NAND (universal gate) as our point of focus. We have compared the leakage value of the proposed NAND gate with the leakage of the normal NAND gate. Maximum leakage saving has been obtained more than 90%. The technique is also well suited for the reduction of dynamic power. Simulation results show up to 63.6% in dynamic power saving with small area and delay overhead.