Design of a 10-bit Segmented Current-Steering CMOS D/A Converter for High Speed Communication System

Autor/innen

  • Anil K. Saini CSIR-Central Electronics Engineering Research Institute
  • Sanjay Singh CSIR-Central Electronics Engineering Research Institute

Schlagwörter:

Digital-to-analog converters, binary weighted, matching, current-steering, CMOS

Abstract

 In the present work, design of a 10-bit digital-to-analog (D/A) converter using current segmentation architecture in 0.35 µm double-poly, four-metal, CMOS process has been attempted. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.8 and 2.5 least significant bits (LSBs) respectively. For sampling frequency of 12-MSample/s, the spurious free dynamic range (SFDR) is better than 56 dB for signal up to Nyquist rate. The worst case power consumption is 58 mW and it operates with a single supply voltage of 3.3. 

Autor/innen-Biografien

  • Anil K. Saini, CSIR-Central Electronics Engineering Research Institute
    ScientistIC DesignCSIR-CEERIPilani, Raj-333031
  • Sanjay Singh, CSIR-Central Electronics Engineering Research Institute
    ScientistIC DesignCSIR-CEERIPilani, Raj-333031

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Veröffentlicht

2012-12-20

Ausgabe

Bd. 2 Nr. 3 (2012)

Rubrik

Research Articles

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