All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey

Autor/innen

  • Rajesh Yadav Department of Electrical and Electronics Engineering, ITM University, Gurgaon, Delhi-NCR, India
  • Neeraj Kumar Shukla Department of Electrical and Electronics Engineering, ITM University, Gurgaon, Delhi-NCR, India
  • Rajesh Gupta Cadence Design System, Noida, Delhi-NCR, India

Abstract

An all-digital phase locked loop (ADPLL) plays a great role in decreasing the developmenttime of an application-specified integrated circuit (ASIC) products and helps to meet the timetomarket requirement of product, because an ADPLL can be used as an IP core, so it is easilyreusable in any design. Now a days ADPLL is being widely used in various fields such ascontrol systems and digital communication systems. This survey paper presents the basicdetails of ADPLL and its recent developments in ADPLL. Implementation and function ofeach component of ADPLL has been described separately.Keywords: ADPLL, DCO, frequency phase detector, loop filter, HDL, SoC, IP coreCite this ArticleRajesh Yadav, Neeraj Kumar Shukla,Rajesh Gupta. All-Digital PhaseLocked Loop (ADPLL) as anIntellectual Property (IP) Core for anApplication-Specified IntegratedCircuit (ASIC) Product: A Survey.Journal of VLSI Design Tools andTechnology. 2015; 5(3): 12–17p.

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2015-10-12

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Bd. 5 Nr. 3 (2015)

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Review Articles

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