Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence

Autor/innen

  • J. K. Arya Department of Electronics and Communication Engineering, National Institute of Technology Jalandhar, Punjab, India
  • A. Raman Department of Electronics and Communication Engineering, National Institute of Technology Jalandhar, Punjab, India

Abstract

Fast growing field of IC technology is persistently demanding for low power consumption and efficient solution. Most of the available SRAM designs are based on standard 6T SRAM cell in addition to other circuit and transistors count. A novel 5T CMOS SRAM is presented in this paper, for simultaneously minimizing power consumption and an improving process speed. The presented unique 5T SRAM cell employs single bitline for read/write function. Implementation of single bitline reduces the power dissipation. Stability and efficiency are improvised by separating the data storage nodes from single bitline during read process. Dynamic power consumption and static power consumption are ameliorated by 28.8 % and 32.7 % respectively. Validation and comparison is performed using cadence spectre.   Keywords: Data stability, leakage power, dynamic power, dual threshold method,  static noise marginCite this Article Arya and Raman. Design of single bitline novel 5T SRAM cell to reduce the power dissipation using cadence. Journal of VLSI Design Tools and Technology. 2016; 6(1): 49–54p.

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Veröffentlicht

2016-02-15

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Bd. 6 Nr. 1 (2016)

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Research Articles

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