Implementation and Simulation of High Speed Dynamic Latch Comparator for ADC

Autor/innen

  • Jatin A. Jajal Department of Electronics and Communication, Marwadi Education Foundation Group of Institute, Rajkot, Gujarat, India
  • Mehul L. Patel Department of Electronics and Communication, Marwadi Education Foundation Group of Institute, Rajkot, Gujarat, India

Abstract

As per emerging issues in analog-mixed signal (AMS) design towards high speed and low power, limits the performance of high-speed applications. Circuit complexity, speed, offset voltage and resolutions are essential parameter of comparator that affects the Analog-to-Digital Converter (ADC) performance. Based on specifications, to achieve lower offset voltage and higher load drivability of latched comparator is presented. Moreover, the circuit is able to reduce power dissipation as the topology is based on latch circuitry.  Resistor-divider structure was used to design a CMOS comparator in TSMC 180 nm technology due to advantage of high speed and no static power consumption. Here, systematic offset voltage is simulated. Achieved parameters are 1.2 GHz sampling rate, above 8 bit resolution, 98 ps propagation delay, 20 mV offset voltage and 77 µW power consumption. In the end, layout was prepared on pyxis (Mentor Graphics) tool.   Keywords: Analog-to-Digital Converter (ADC), dynamic latch comparator, offset voltage, sampling rateCite this Article Jatin A. Jajal, Mehul L. Patel. Implementation and Simulation of High Speed Dynamic Latch Comparator for ADC. Journal of VLSI Design Tools and Technology. 2016; 6(2): 99–103p.

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2016-08-12

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Bd. 6 Nr. 2 (2016)

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Research Articles

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