Low-Power Design of Content Addressable Memory using Master Slave Match Line Architecture

Autor/innen

  • Boda Venkata Lakshmi Department of Electronics and Communication Engineering, Pydah College of Engineering and Technology, Visakhapatnam, Andhra Pradesh, India
  • Boggavarapu Satish Kumar Department of Electronics and Communication Engineering, Pydah College of Engineering and Technology, Visakhapatnam, Andhra Pradesh, India

Abstract

Content Addressable Memory (CAM) is a storage unit used for faster accessing of lookup table that reduces processing time for search operation. It is mainly used very-high-speed searching applications like computer networking devices. The MAC address table is implemented with a CAM so that the destination port can be easily detected by reducing the switch’s latency. CAM gets its high speed of operation by parallel search mechanism. This paper proposes a CAM with master slave match line architecture. It uses a 128 ´ 8 CAM with reduced voltage swing to minimize power consumption. Complete memory is searched simultaneously for decreasing the time needed for search operation. Hence, computational time gets reduced appreciably. The performance of CAM is estimated by computing the power consumption and match delay. The results are analysed and compared for various match cases. HSPICE along with Cosmoscope is used to simulate and view the waveforms respectively.   Keywords: HSPICE, CAM, Match delay and MSML  Cite this Article Boda Venkata Lakshmi, Boggavarapu Satish Kumar. Low-Power Design of Content Addressable Memory using Master Slave Match Line Architecture. Journal of VLSI Design Tools and Technology. 2017; 7(1): 29–34p.

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Veröffentlicht

2017-03-23

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Bd. 7 Nr. 1 (2017)

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Research Articles

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