Decimator Design for Sigma-Delta ADC

Authors

  • Tripti Sharma Worked for her M Tech. (Microelectronics & VLSI Design) dissertation at CEERI.
  • Prashant Singh Worked for his M Tech. (Microelectronics & VLSI Design) dissertation at CEERI
  • Narendra Bahadur Singh Central Electronics Engineering Research Institute (CEERI-CSIR).

Keywords:

DSP, decimator, counter, sigma-delta ADC, DAC, operational amplifier

Abstract

This paper describes the design of a decimator which is used in digital signal processing as well as 10-bit sigma-delta analog-to-digital converter to down sample the incoming signal for further applications. It is also used for verification of the sigma-delta modulator functionality to reconstruct the incoming signal. The design has been carried out using 180 nm TSMC, CMOS foundry parameters for spice level 49 model parameters in TANNER EDA (Tspice). The results for the presented decimator model are mentioned in the paper; the higher decimation factor can be taken similarly as per requirement.

Author Biographies

  • Tripti Sharma, Worked for her M Tech. (Microelectronics & VLSI Design) dissertation at CEERI.
    Work carried out during her M Tech. (Microelectronics & VLSI Design) Final dissertation at CEERI.
  • Prashant Singh, Worked for his M Tech. (Microelectronics & VLSI Design) dissertation at CEERI
    Work carried out during his M Tech. (Microelectronics & VLSI Design) Final dissertation at CEERI.
  • Narendra Bahadur Singh, Central Electronics Engineering Research Institute (CEERI-CSIR).
    In-charge MEMS,MS & RF ICs Design Lab, Senior Principal Scientist. More than 28 Years R&D Experience in MS/RF ICs,MEMS,Memory,Image Codec,AES,DES ASICs Design, IC Testing after fabrication and IT areas.

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Published

2012-05-11

Issue

Vol. 2 No. 1 (2012)

Section

Review Articles

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