Delay Minimization of 3 Cascaded Inverters with the Help of Logical Effort and Transistor Sizing

Authors

  • Sampath Kumar V.
  • neerja Singh I am mtech(vlsi design) student of jss academy of technical education ,noida

Keywords:

effort, 3 cascaded inverters, capacitance

Abstract

 With logical effort minimum delay of the path can be estimated by only knowing number of stages, path effort, and parasitic delay without the need to assign transistor sizes. This is superior to simulation where delay depends on sizes and you never achieve certainty that the size selected would offer minimum delay. In this work 3 cascaded inverters is being sized in the ratio 1:2:3 to achieve minimum propagation delay and comparison is made with the 3 cascaded inverter not sized in the ratio 1:2:3. 

Author Biography

  • Sampath Kumar V.
    I am mtech(vlsi design) student of jss academy of technical education ,noida

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Published

2012-05-11

Issue

Vol. 2 No. 1 (2012)

Section

Research Articles

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