Real Time FPGA-based Embedded Architecture of Audio Compression and Decompression Core for Multimedia System

Authors

  • Moumita Acharya Deparment of VLSI, C.V.Raman College of Engineering, Bhubaneswar, Odisha, India
  • Shreedeep Gangopadhyay Department of Electronics & Communication Engineering, Techno India, Saltlake, Kolkata, West Bengal, India

Abstract

A multimedia system links images and audio to distribute and transmit information to users. These images and audio data have to be compressed for raising capacity of storing and processing tasks in real time without losing the required information. This paper introduces an audio processing unit by using the FPGA hardware board. This is a complete Embedded system where the audio compression and decompression core is firstly described as a functional specification in VHDL and then it is synthesized, compiled and simulated on Xilinx ISE 12.4/13.1 software and finally, it is implemented on the hardware of Virtex-5 (ML506) FPGA using Microblaze processing core on EDK/SDK environment. This system will receive a song from mobile in MP3 format and process the audio file by using the AC97 Codec, available in the FPGA board. Finally, the song will be stored in the FPGA board and will be played back in real time by using the headphones connected to the hardware target board.   Keywords: FPGA, MP3, AC97 Codec, lossy compression, Virtex5, VHDL, EDK/SDKCite this Article:  Acharya M, Gangyopadhay S. Real Time FPGA Based Embedded Architecture of Audio Compression and Decompression Core for Multimedia System. Journal of VLSI Design Tools and Technology (JoVDTT). 2015; 5(1): 34–44p.

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Published

2015-03-10

Issue

Vol. 5 No. 1 (2015)

Section

Research Articles

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