High-speed CMOS ADCs Design

Autores/as

  • Prashant Singh Worked as a Trainee in MEMS,MS & RF ICs Design Lab at CSIR-CEERI.
  • Narendra Bahadur Singh Senior Principal Scientist,MEMS MS & RF ICs Design, Semiconductor Devices Area,Central Electronics Engineering Research Institute(CSIR-CEERI), Pilani, Rajasthan-333031.

Palabras clave:

Flash and subranging ADC, operational amplifier, comparator and subtractor

Resumen

This paper presents the design of high-speed subranging and flash analog to digital data converters (ADC) including the design of efficient operational amplifier to meet the performance requirements of these data converters for the specifications laid down targeted to the SCL 1.2 μm CMOS Foundry. The design starts from the specification of the circuit, its theoretical analysis for the parameter estimations of the transistors as well as the circuit’s design. Its simulation studies with design iterations were carried out using EDA tools. Pre- and post-layout electrical behavior verification of the circuit was carried out for the circuits from its layout as well as netlist extracted circuit from its schematic. Best performance has been achieved by the design iterations as presented in the paper.

Biografía del autor/a

  • Prashant Singh, Worked as a Trainee in MEMS,MS & RF ICs Design Lab at CSIR-CEERI.
    B Tech in ETE and M Tech in Microelectronics & VLSI Design.
  • Narendra Bahadur Singh, Senior Principal Scientist,MEMS MS & RF ICs Design, Semiconductor Devices Area,Central Electronics Engineering Research Institute(CSIR-CEERI), Pilani, Rajasthan-333031.
    Deaprtment: MEMS/MS/RF CMOS IC DesignDesignation:Senior Principal ScientistTel No: +91-1596-252281, Mobile: +91 9414883889.Current R&D Area:  MEMS,Analogue,Digital, Memory,MS,RF CMOS IC Design & Testing. Bio: More than 29 Years of R&D Experiences on Analogue (12/16 bit SA,SD,Flash & SR ADCs/DACs, PLL/VCO/Sensor’s Signal Conditioners), Digital & RF CMOS Full Custom ICs Design, PSDRAM/SRAM Full Custom Chip Design, Micro Sensors (MEMS) Design, IEEE-754 Compatible Numeric Processor Design, AES/DES with enhanced key feature Cryptography System Design for Secured data  Communication, JPEG Codec Design, ATPG Development, QPSK/ASK/AM TRx/Modem system modelling and CMOS Circuits Design. Experience on front and back end VLSI Design tools, IC Test setup development and testing, Integration of I/O’s on FPGA and its testing in board. Numerical Simulation and High Speed Device modelling. CMOS Circuit/Device/IC Process Simulation and Modeling. Work Experience on semiconductor processes, like Metallization, RTP, Etching and Lithography. Neural Networks for Pattern Learning and Fuzzy Rule based Expert System Shell development. Knowledge and extensive work experience on of all Computer languages and micro/mini/main frame/embedded systems. Experience on Management of Computers on LAN, ECAD, mail, squid and proxy servers. More than 30 papers in journals as well as international conferences. ME in Microelectronics Teaching experience in BITS. Supervised More than 27 M Tech 1 year dissertations in Microelectronics & VLSI Design and 50 B Tech/ M Sc/ MCA dissertations for six months.  

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Publicado

2012-05-11

Número

Vol. 2 Núm. 1 (2012)

Sección

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