Methodology of Standard Cell Library Design in .LIB Format

Autores/as

  • Arindam Sadhu Department of Electronics & Communication Engineering - Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, India
  • Pritam Bhattacharjee Department of Electronics & Communication Engineering - Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, India

Palabras clave:

250 nm technology GPDK, standard-cell library design, .lib formulated characterization

Resumen

The importance of standard cell library design methodology is growing with very-large-scale integration (VLSI) technology advancement due to its usage in VLSI EDA synthesis flows. In this paper, to best of our knowledge and information in any published literature no systematic method of standard cell and creating appropriate co-laterals. In this paper the standard cell design methodology, layout topology, methodology for creating characterized timing table has been developed using 250 nm technology GPDK. This method can be easily reused in deep sub-micron technology for appropriate co-laterals. In addition a new methodology of reusing standard cell for full custom design has been proposed in this paper.

Biografía del autor/a

  • Arindam Sadhu, Department of Electronics & Communication Engineering - Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, India
    B-Tech (Electronics & Communication Engineering) and M-Tech (VLSI) from West Bengal University of Technology and pursuing Ph.D at West Bengal University of Technology under Dr. Debashis De, Associate Professor, Computer Science Engineering department, WBUT.
  • Pritam Bhattacharjee, Department of Electronics & Communication Engineering - Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, India
    B-Tech (Electronics & Communication Engineering) and M-Tech (VLSI) from West Bengal University of Technology

Descargas

Publicado

2014-03-28

Número

Vol. 4 Núm. 1 (2014)

Sección

Case Study

Licencia

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