Design and Implementation of an Efficient Ternary Control Unit

Autores/as

  • SS Narkhede Department of E&TC, Pune Institute of Computer Technology, SP Pune University, India
  • BS Chaudhari Department of E&TC, Maharashtra Institute of Technology, SP Pune University, India
  • GK Kharate Department of E&TC, Matoshri College of Engineering, SP Pune University, India

Resumen

Multi-valued logic (MVL) is emerging as a thrust area of research due to several advantages offered by them over the conventional binary logic. Ternary logic is a promising alternative to the binary logic design technique thereby attracting a wide community of researchers to contribute in the design of ternary processor. The control unit is effectively the nerve center of a processor that plays a vital role in generating the appropriate control signals and synchronizing all the operations. Design of a control unit is, therefore, the most crucial aspect in processors which have received meager attention in the literature from the ternary perspective. This paper presents design and implementation of an efficient ternary control unit (TCU) for a ternary processor using very-high-speed integrated circuits, and VHSIC hardware description language (VHDL). The functionality of the TCU is verified using sixty-five instructions belonging to various addressing modes. The control signals required for the execution of the instructions are identified and further modeled using VHDL. The paper shows the potential of VHDL modeling and simulation that can be applied to TCU. The extensive simulation results of the designed TCU signify encouraging results that will pave the path for further developments in ternary processors.   Keywords: Multi-valued logic, ternary logic, control unit, VHDLCite this Article Narkhede SS, Chaudhari BS, Kharate GK. Design and implementation of an efficient ternary control unit. Journal of VLSI Design Tools and Technology. 2015; 5(3): 55–70p.

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Publicado

2015-10-12

Número

Vol. 5 Núm. 3 (2015)

Sección

Research Articles

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