VHDL Implementation of 4 Bit Multipliers: Comparative Study with Vedic Multiplier

Auteurs-es

  • M A Sayyad Department of Electronics and Telecommunication Engineering, SRES COE, Kopargaon, Savitribai Phule, Pune University, India
  • U R Chaware Department of Electronics and Telecommunication Engineering, SRES COE, Kopargaon, Savitribai Phule, Pune University, India

Résumé

The multiplier and adder are the basic building blocks of ALU of any processor and speed of this processor are greatly depends on these building blocks. The performance of multipliers can be analyzed using its performance parameters like speed, power consumption, complexity, etc. In digital signal processors as well as in general processors high speed can be achieved using this multiplier block. The Vedic multiplier architecture exhibits speed improvements and Reversible computing will lead to improvement in energy efficiency.   Keywords: Vedic mathematics, Urdhva-Triyagbhyam, Reversible logic Cite this Article Sayyad MA, Chaware UR. VHDL Implementation of 4 Bit Multipliers: Comparative Study with Vedic Multiplier. Journal of VLSI Design Tools and Technology. 2015; 5(3):   122–127p.

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Publié

2015-11-05

Numéro

Vol. 5 No. 3 (2015)

Rubrique

Research Articles

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