Design of 16-bit Pipelined RISC Processor

Autori

  • Kalyan Acharjya Worked for M Tech dissertation at CEERI, Pilani.
  • N. B. Singh Central Electronics Engineering Research Institute (CEERI-CSIR).

Parole chiave:

Processor, RISC, Pipelined and HDL

Abstract

This paper presents the design of efficient and high throughput 16-bit pipelined RISC Processor. The design is challenge with the pipelined stall problem, speed with external memory, coding density and clock frequency for cost effectiveness and higher performance processor design. Paper describes about the architecture, programming model, synthesis results and analysis of the design. The presented design has throughput ~167 MIPS at 500 MHz, which shows better performance at a particular frequency.  The coding is carried out in Verilog HDL and functionality is verified through simulation and test benches at different stages including behavioral and gate level RTL code using Modelsim (Mentor Graphics). The synthesis part is done using Leonardo Spectrum (Mentor Graphics) and implementation done in Xilinx ISE 9.1.  

Biografia autore

  • N. B. Singh, Central Electronics Engineering Research Institute (CEERI-CSIR).
    In-charge MEMS,MS & RF ICs Design Lab, Senior Principal Scientist in CSIR-CEERI. 28 Years R&D experiences on Analogue,Digital,MS,RF & Memory CMOS ICs Design & Testing, Test Setup Dev. Image Code, IEEE-754 Processor, AES & DES ASICs Design, IC Process Technology, Simulation & Modelling of Devices,uC and IT areas.  

Dowloads

Pubblicato

2012-09-09

Fascicolo

V. 2 N. 2 (2012)

Sezione

Research Articles

Licenza

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