Performance Estimation of VLSI Design

Autori

  • Arindam Sadhu Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India
  • Pritam Bhattacherjee Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India
  • Sabnam Koley Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India

Parole chiave:

Propagation delay, NMOS, PMOS, Rise Time, Fall Time, Elmore Delay, Layout.

Abstract

This paper explores performance estimation of VLSI design using simple RC delay model based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow for delay convergence is also shown.   Keyword: Propagation delay, NMOS, PMOS, Rise Time, Fall Time, Elmore Delay, Layout

Pubblicato

2014-08-26

Fascicolo

Sezione

Review Articles