Comparative Analysis of High Speed Comparator for A to D Converters

Autori

  • Priyesh P. Gandhi Department of Electronics and Communications, Institute of Technology, Nirma University, Ahmedabad, Gujarat, India
  • Neha B. Rathod Department of Electronics and Communications, L.C. Institute of Technology, Bhandu, Gujarat, India
  • N. M. Devashrayee Department of Electronics and Communications, Institute of Technology, Nirma University, Ahmedabad, Gujarat, India

Abstract

In this paper dynamic comparator along with the output buffer stage has been introduced. The simulation is carried out in 130 and 90 nm technologies. The supply voltage for 130 nm is 1.3 V and for 90 nm is 0.9 V. Different analyses for various characteristics of the comparator such as ICMR, delay, offset voltage and power dissipation is carried out in 130 and 90 nm CMOS technology. The comparator benefits from two stages and two operational phases to reduce the offset voltage caused by the mismatch inside the positive feedback circuit. The simulation result shows speed 6.71 and 5.04 GHz with the power dissipation 13.04 and 86.11 µW in 90 and 130 nm technologies respectively. The power consumption and offset voltage of the comparator present in this paper is less in comparison to conventional comparator. The simulation results allow the circuit designer to fully explore the tradeoffs in comparator design.   Keywords: CMOS, MOSFET, comparator, ICMR, offset voltage, power dissipationCite this Article  Gandhi Priyesh P, Rathod Neha B, Devashrayee N.M. Comparative Analysis of High Speed Comparator for A to D Converters. Journal of VLSI Design Tools and Technology (JoVDTT). 2015; 5(2): 4–10p.

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Pubblicato

2015-05-06

Fascicolo

V. 5 N. 2 (2015)

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Research Articles

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