Challenges beyond 100 nm MOS devices

Autori

  • Savita Maurya Integral University, Lucknow
  • Sarita Shrivastava Integral University, Lucknow

Parole chiave:

MOS technology, device scaling, semiconductor manufacturing

Abstract

MOS devices have been aggressively scaled down in research and in production in last few years. Sub-100 nm feature size MOS circuits have been used for many. However, many serious limitations and problems emerged with such a small geometry MOSFETs are used to realize very large-scale integrated circuits. Commercial 45 nm technology node, has much higher production cost and it is one of the greatest concern for scaling down devices beyond 10 nm. This paper deals with challenges and limits of beyond 100 nm technology. Possible limiting factors for the scaling of devices have also been elaborated.

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Pubblicato

2016-06-07

Fascicolo

V. 6 N. 2 (2016)

Sezione

Research Articles

Licenza

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