V. 5 N. 3 (2015)

Pubblicato: 2015-10-05

Research Articles

CMOS Gm-C IF Filter using SCA for Dual Band Receiver

Kehul A Shah, N M Devashrayee

18-36
- Accesso riservato PDF (inglese) (USD 20)
Design and Performance Analysis of Multi-Standard CMOS LNA Using Switched Capacitor and MIM Capacitor in 180nm Technology

Nishant Poras, Priyanka Goyal

37-44
- Accesso riservato PDF (inglese) (USD 20)
Memristor Modelling for Common Source Amplifier Using 180 nm Technology

Herman Al Ayubi, Navaid Z. Rizvi, Piyush Kumar Mishra

45-54
- Accesso riservato PDF (inglese) (USD 20)
Design and Implementation of an Efficient Ternary Control Unit

SS Narkhede, BS Chaudhari, GK Kharate

55-70
- Accesso riservato PDF (inglese) (USD 20)
Effect of Inter Shell Spacing on Performance of MWCNT Bundle at 100 Âµm Interconnect Length

Akshi Acharya, Abhishek Shrivastava, Gaurav Musalgaonkar

71-79
- Accesso riservato PDF (inglese) (USD 20)
Development of High Impedance Current Mirror Circuit With Its Implementation Using 0.18 Î¼m Technology

Haresh P. Patani, Nilesh D. Patel

87-96
- Accesso riservato PDF (inglese) (USD 20)
FPGA Implementation of Binary Integer Decimal based Floating Point Multiplier

Priyanka Rani, Sakshi Bajaj

97-103
- Accesso riservato PDF (inglese) (USD 20)
Implementation of LMS Calibration Algorithm for 12-Bit Pipelined ADC

Vishali ., Alpana Agarwal

104-113
- Accesso riservato PDF (inglese) (USD 20)
VHDL Implementation of 4 Bit Multipliers: Comparative Study with Vedic Multiplier

M A Sayyad, U R Chaware

122-127
- Accesso riservato PDF (inglese) (USD 20)
Development of High Slew-Rate CMOS Operational-Amplifier

Chilka S Patel, Priyesh P Gandhi

128-131
- Accesso riservato PDF (inglese) (USD 20)
Implementation of Register Access Methods for Device Configuration Using UVM

Jyoti Dahiya, Neeraj K. Shukla

132-138
- Accesso riservato PDF (inglese) (USD 20)
Implementation of Sub Parts of SAR ADC

Purvi J Patel, Priyesh P Gandhi

139-147
- Accesso riservato PDF (inglese) (USD 20)

Review Articles

A Review on Charge Pump Circuits for PLL Applications

D. Shekhar, A. Raman

1-11
- Accesso riservato PDF (inglese) (USD 20)
All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey

Rajesh Yadav, Neeraj Kumar Shukla, Rajesh Gupta

12-17
- Accesso riservato PDF (inglese) (USD 20)
A Real Time Authentication Framework Using Multi-Model Biometrics

Sneha Kurhekar, Harshvardhan Upadhyay

80-86
- Accesso riservato PDF (inglese) (USD 20)
Roles and Responsibilities of Verification Language, Verification Methodology and Verification Tool for Design Verification of a DUT

Rakhi Nangia

114-121
- Accesso riservato PDF (inglese) (USD 20)

V. 5 N. 3 (2015)

Research Articles

CMOS Gm-C IF Filter using SCA for Dual Band Receiver

Design and Performance Analysis of Multi-Standard CMOS LNA Using Switched Capacitor and MIM Capacitor in 180nm Technology

Memristor Modelling for Common Source Amplifier Using 180 nm Technology

Design and Implementation of an Efficient Ternary Control Unit

Effect of Inter Shell Spacing on Performance of MWCNT Bundle at 100 Âµm Interconnect Length

Development of High Impedance Current Mirror Circuit With Its Implementation Using 0.18 Î¼m Technology

FPGA Implementation of Binary Integer Decimal based Floating Point Multiplier

Implementation of LMS Calibration Algorithm for 12-Bit Pipelined ADC

VHDL Implementation of 4 Bit Multipliers: Comparative Study with Vedic Multiplier

Development of High Slew-Rate CMOS Operational-Amplifier

Implementation of Register Access Methods for Device Configuration Using UVM

Implementation of Sub Parts of SAR ADC

Review Articles

A Review on Charge Pump Circuits for PLL Applications

All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey

A Real Time Authentication Framework Using Multi-Model Biometrics

Roles and Responsibilities of Verification Language, Verification Methodology and Verification Tool for Design Verification of a DUT

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