V. 6 N. 3 (2016)

Visualizza V. 6 N. 3 (2016)

Pubblicato: 2016-10-21

Research Articles

Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy

Shashank Gautam, Pramod Sharma

1-6
- Accesso riservato PDF (inglese) (USD 20)
Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier

Saguna Goel, Sakshi Bajaj, Amanpreet Kaur

7-14
- Accesso riservato PDF (inglese) (USD 20)
Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers

Akash I. Mecwan, N M Devashrayee

22-27
- Accesso riservato PDF (inglese) (USD 20)
Development of System for Speech Enhancement using Combinational Adaptive LMS on Reconfigurable Platform

Pradip C. Bhaskar, Prachi S. Gosavi

28-34
- Accesso riservato PDF (inglese) (USD 20)
A Unified Ultra Low Power Architecture of Probabilistic Adder Based on GDI Technique

Srinibasa Padhy, Shivalal Patro, Monica Swain, Jitendra Kumar Das

45-55
- Accesso riservato PDF (inglese) (USD 20)
Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications

Ankush Chunn, Rakesh Kumar Sarin

71-87
- Accesso riservato PDF (inglese) (USD 20)
VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter

Minakshi Motiram Wanjari, Pankaj Agrawal, Ravindra Kshirsagar

88-93
- Accesso riservato PDF (inglese) (USD 20)

Review Articles

Design of FPGA Based ALU Using Reversible Logic Gates

Vishal A. Wankhede, Ramprasad M. Gawande

15-21
- Accesso riservato PDF (inglese) (USD 20)
Survey of System-on-Chip Modular Test Approach

Harpreet Vohra, Amardeep Singh

56-70
- Accesso riservato PDF (inglese) (USD 20)

Short Articles

Design of High-Speed and Low-Power Carry Skip Adder

Gutlapalli Venkatrao, Motkuri Krishna

35-44
- Accesso riservato PDF (inglese) (USD 20)