Performance Estimation of VLSI Design

著者

  • Arindam Sadhu Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India
  • Pritam Bhattacherjee Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India
  • Sabnam Koley Microelectronics & VLSI, Heritage Institute of Technology, Kolkata, W.B., India

キーワード:

Propagation delay、 NMOS、 PMOS、 Rise Time、 Fall Time、 Elmore Delay、 Layout.

要旨

This paper explores performance estimation of VLSI design using simple RC delay model based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow for delay convergence is also shown.   Keyword: Propagation delay, NMOS, PMOS, Rise Time, Fall Time, Elmore Delay, Layout

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発行日

2014-08-26

巻号

巻 4 号 2 (2014)

セクション

Review Articles

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