A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture

著者

  • Ashish S. Shende P.G. Department of Electronics Engineering, Bapurao Deshmukh College of Engineering, Sewagram, Maharashtra, India
  • Deepak R. Dandekar P.G. Department of Electronics Engineering, Bapurao Deshmukh College of Engineering, Sewagram, Maharashtra, India

キーワード:

Multi-Valued Logic、 Current-Mode Circuits、 Vedic Multiplier、 Urdhva Tiryakbhyam Sutra、 Digital Signal Processing

要旨

A multiplier is a fundamental block of any digital signal processing system. Urdhva Tiryakbhyam sutra, from ancient Indian Vedic mathematics, offers regular and hierarchical multiplier architecture. Alternatively, current-mode multi-valued logic results in reduced circuitry and effective utilization of interconnections. In this paper, a new 4×4 current-mode quaternary Vedic multiplier design is proposed. The multiplier has been simulated using 0.18 µm technology with a power supply of 1 V and a unit current step of 1 µA. The proposed multiplier works on simple quaternary arithmetic and has a very low transistor-count. The transient delay of the proposed multiplier also has been improved compared to our previous multiplier. The proposed approach of employing multi-valued logic with Vedic architecture has made the application of multi-valued logic simpler, which can make multi-valued circuits as generalized as binary circuits.   Keywords: Multi-Valued Logic, Current-Mode Circuits, Vedic Multiplier, Urdhva Tiryakbhyam Sutra, Digital Signal Processing

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発行日

2014-08-26

巻号

巻 4 号 2 (2014)

セクション

Research Articles

ライセンス

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